Design verification by test vectors and arithmetic transform Universal Test Set
نویسندگان
چکیده
منابع مشابه
Hardware Verification by Universal Test Set Simulations, Sat and Bdds
In this paper we consider verification of combinational circuits by test vector simulations. The simulation-based verification under the presence of a fault model uses test pattern generation approach. We consider an implicit fault model that can possibly overcome incompleteness of explicit fault models considered so far. We show that the test vector generation can be enhanced by techniques use...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computers
سال: 2004
ISSN: 0018-9340
DOI: 10.1109/tc.2004.1275301